Power consumed by leakage currents in system on a chip (SoC) ASIC designs has become a large portion of the overall power budget of the SoC designs. One approach to reduce an SoC's leakage current is to vary the gate length of transistors in standard cells that are utilized to create the SoC due to the fact that an exponential relationship exists between a standard cell's source-drain leakage and its gate length.
Standard cell libraries typically include low leakage cells (LOLK) for a circuit designer to utilize in a circuit design. Every transistor in a low leakage cell has an increased gate length to provide a substantial decrease in leakage current, referred to as “upsized” transistors. However, these low leakage cells are typically 10-15 percent larger than the default standard cell because of the larger gate lengths throughout the cell, and are typically slower than the default standard cell because of the substantial decrease in leakage current. As such, a circuit designer is required to evaluate tradeoffs between using default standard cells that are smaller, faster, but have high leakage current versus low leakage cells that have low leakage current but are larger and slower.